Clock generation for digital systems generally requires clock frequencies that are stable, and in many cases the digital system clock frequencies are related by integer multiples. Typically, the master clock starts as the output of a crystal-controlled oscillator, then a digital version of the oscillator output is generated by various shaping circuits. These shaping circuits provide fast rise and fall times as well as symmetry between the two halves of the clock period. To generate clock signal symmetry, sometimes a higher frequency clock is divided down with a flip flop circuit to generate a clock with symmetrical half periods. In this method, various low frequency clocks may be generated from the master clock by again dividing down the master clock.
Many times, a phase lock loop (PLL) is used with a voltage-controlled oscillator (VCO) in a feedback loop to generate a high frequency clock from a lower frequency clock. In this way, the stable master clock is of a lower frequency which may be easier to generate. If the clock is for a digital processing system employing a central processor unit (CPU), which executes instructions relative to the clock period, then there are times when it is desirable to have certain functions of the CPU executing on sub-portions of the clock period, for example, on each half or quarter cycle. Having a stable high frequency clock where the clock period may be broken up into precise sub-periods is very desirable in operations within a computer and in various data recovery schemes used in digital communication.
One prior art way of generating M-multiple phases of a clock is to use a PLL employing a voltage-controlled oscillator (VCO) and a phase detector. The reference clock, of frequency F, is the input to the PLL, and the output frequency of the VCO is divided by M and compared to the reference clock in a phase comparator. Since the PLL may control the high frequency (Mxc3x97F) clock so it is phase and frequency locked with the input :reference clock, the transitions of the high frequency clock may be used to generate multiple phases of the reference clock. As clock frequencies become very high, generating an M times higher frequency clock, as a way of generating many multiple phases, may become prohibitive as M becomes larger (e.g., 5 to 10).
There is, therefore, a need for a way to generate M multiple phases of a high frequency clock of a frequency F using a reference clock with a frequency lower than normally required for a prior art multiphase clock generation.
A multiphase voltage-controlled oscillator (MPVCO) is used with a multiphase (MiP) phase detector in a feedback configuration to generate specific multiple phase clocks that are phase and frequency locked to a reference clock. The MPVCO is used with corresponding logic circuits to generate a quadrature reference clock without generating frequencies higher than the reference clock. Another MPVCO is designed with a frequency of only two times higher than a reference clock, and with corresponding logic circuits generates 4xc3x97M equal phases of the reference clock where M is an integer characteristic of the MPVCO. In one exemplary embodiment of the present invention, M is equal to five and twenty phases of the reference clock may be generated.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention.